1. Field of the Invention
The present invention is related to flash memory devices/systems, and more particularly, to programming multi-state flash memory cells.
2. Background of the Invention
Semiconductor memory devices have become popular for use in various electronic devices. For example, non-volatile semiconductor memory is used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices and other electronic devices. Electrical Erasable Programmable Read Only Memory (EEPROM) and flash memory are among the most popular non-volatile semiconductor memories.
One example of a flash memory system uses the NAND structure, which includes arranging multiple transistors in series, sandwiched between two select gates. A NAND array has a number of memory cells (or storage units, used interchangeably throughout this specification), such as 4, 8, 16, or even 32, connected in series string (NAND string) between a bit line and a reference potential through select transistors at either end. Word lines are connected with control gates of cells in different series strings. Relevant examples of NAND arrays and their operation are given in the following U.S. patents that are incorporated herein in their entirety by this reference: U.S. Pat. Nos. 5,570,315, 5,774,397 and 6,046,935.
Flash memory cells can be dual state or multi state. A dual state (2LC) memory cell stores 1 bit of data, while multi-state memory cells can store more data. Current NAND technology can support a 4 state (4LC) memory cell, which can store 2 bits of data. Briefly, two bits of data from different logical pages of incoming data are programmed into one of four states of the individual cells in two steps, first programming a cell into one state according to one bit of data and then, if the data makes it necessary, re-programming that cell into another one of its states according to the second bit of incoming data.
As technology improves, future NAND cells could handle 6 state (6LC), 8 state (8LC) or even 16 state (16LC) memory cells. Programming multi-state memory cells has challenges, especially for a 3 state or a 6 state memory cell. A 3 state memory cell could store 1.5 bits and a 6 state memory cell could store 2.5 bits. Complex calculation circuits will be required to maintain the book-keeping for storing 0.5 bit increments.
Furthermore, during the operation of a non-volatile memory, reading and writing of data in one memory will often disturb the data stored in other memory cells. One source of these disturbs is the field effect coupling between adjacent floating gates as described in U.S. Pat. No. 5,867,429 of Jian Chen and Yupin Fong, which patent is incorporated herein in its entirety by this reference. The degree of these coupling increases as the size of memory cell arrays is being decreased as the result of improvements of integrated circuit manufacturing techniques. The problem occurs most pronouncedly between two sets of adjacent cells that have been programmed at different times. One set of cells is programmed to add a level of charge to their floating gates that corresponds to one set of data. After the second set of cells is programmed with a second set of data, the charge levels read from the floating gates of the first set of cells often appears to be different than programmed because of the effect of the charge on the second set of floating gates being coupled with the first. This is known as the Yupin effect.
To optimize programming speed/minimum Yupin effect, while maintaining simple logic in a high density multi-state memory cell storing data in 0.5 bit increments (for example, in 3LC and 6LC) is a challenge.